library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
	
	
entity SFT_intf is
	Port ( 
		reset:In STD_LOGIC;
		clk : In STD_LOGIC; 
       --data input port number
       Rcv_SportN: In STD_LOGIC_VECTOR(1 downto 0);
       
       --address FIFO signals  		
        
        afifo_wreq :IN STD_LOGIC ;
        afifo_input : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        
        
        
       --output port number FIFO signals for pfifo
        pfifo_output: out  STD_LOGIC_VECTOR (2 downto 0);     
		pfifo_rdreq : IN STD_LOGIC;
		
		
		TSF_DS_PortNum : In STD_LOGIC_VECTOR (1 downto 0);
		TSF_Bcast: in STD_LOGIC;
		TSF_OutputP_ready: In STD_LOGIC; 
		
		SFT_req_out: Out STD_LOGIC;
		SFT_SportN: Out STD_LOGIC_VECTOR(1 downto 0);
		
			
		SFT_SMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
		SFT_DMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
--    debug output 		
-- 		count_out : Out STD_LOGIC_VECTOR(3 downto 0);
-- 		Mac_reg: Out STD_LOGIC_VECTOR(7 downto 0);
-- 		Dn_reg_en: out STD_LOGIC;
-- 		afifo_r: out STD_LOGIC;
-- 		afifo_out: out STD_LOGIC_VECTOR(7 downto 0);
-- 		count_asset: out STD_LOGIC;
		afifo_ept: out STD_LOGIC;
--		pfifo_ept: out STD_LOGIC;
------debug line 
 				
		SFT_RDone: Out STD_LOGIC
		);
	
end SFT_intf;
	
ARCHITECTURE Behav OF SFT_intf IS	
	Signal	afifo_empty: STD_LOGIC; 
	Signal	afifo_output: STD_LOGIC_VECTOR(7 downto 0);
    Signal	afifo_rdreq:  STD_LOGIC;
    	
--    Signal	pfifo_full:  STD_LOGIC;
    Signal	pfifo_input :  STD_LOGIC_VECTOR (2 downto 0);
	Signal	pfifo_wreq :  STD_LOGIC;
	
component SF_table_interface is
 		Port ( 
		reset:In STD_LOGIC;
		clk : In STD_LOGIC; 
       --data input port number
       Rcv_SportN: In STD_LOGIC_VECTOR(1 downto 0);
       
       --address FIFO signals  		
        Add_Fifo_empty: In STD_LOGIC;
        Add_Fifo_data: In STD_LOGIC_VECTOR(7 downto 0);
        Add_Fifo_rdreq_out : out STD_LOGIC;
       
       --output port number FIFO signals for pfifo
              
--		Outp_Fifo_full: In STD_LOGIC;
		Outp_Fifo_Pdata : Out STD_LOGIC_VECTOR (2 downto 0);
		OutP_Fifo_wreq_out : out STD_LOGIC;
	   --SF-table signals 
		
		TSF_DS_PortNum : In STD_LOGIC_VECTOR (1 downto 0);
		TSF_Bcast: in STD_LOGIC;
		TSF_OutputP_ready: In STD_LOGIC; 
		
		SFT_req_out: Out STD_LOGIC;
		SFT_SportN: Out STD_LOGIC_VECTOR(1 downto 0);
		
			
		SFT_SMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
		SFT_DMac_add_out : Out STD_LOGIC_VECTOR(7 downto 0);
--    debug output 		
-- 		count_out : Out STD_LOGIC_VECTOR(3 downto 0);
-- 		Mac_reg: Out STD_LOGIC_VECTOR(7 downto 0);
--		Dn_reg_en: out STD_LOGIC;
-- 		count_asset: out STD_LOGIC;
        
------debug line 
 				
		SFT_RDone: Out STD_LOGIC
	);
End component;

component Output_FIFO IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
END component;

	
component Add_Fifo IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;

begin
---debug line
--    afifo_r<=afifo_rdreq;
--      afifo_out<=afifo_output;
    	  afifo_ept<=afifo_empty;	
---debug
	TSF_interface: SF_table_interface PORT MAP
    ( 
		reset			=>reset,
		clk	            =>clk,  
       --data input port number
        Rcv_SportN		=>Rcv_SportN,
        Add_Fifo_empty	=>afifo_empty,
        Add_Fifo_data   =>afifo_output,
        Add_Fifo_rdreq_out	=> afifo_rdreq,
       
       --output port number FIFO signals for pfifo
              
--		Outp_Fifo_full	=>pfifo_full,
		Outp_Fifo_Pdata =>pfifo_input,
		OutP_Fifo_wreq_out	=>pfifo_wreq, 
	   --SF-table signals 
		
		TSF_DS_PortNum	=>TSF_DS_PortNum,
		TSF_Bcast		=>TSF_Bcast,
		TSF_OutputP_ready	=>TSF_OutputP_ready, 
		
		SFT_req_out		=>SFT_req_out,
		SFT_SportN		=>SFT_SportN,
		
			
		SFT_SMac_add_out=>SFT_SMac_add_out,
		SFT_DMac_add_out=>SFT_DMac_add_out,
--debug line
--		Mac_reg=>Mac_reg,
--        count_out=>count_out,
--        Dn_reg_en=>Dn_reg_en,
--debug end				
		SFT_RDone		=>SFT_RDone
	);

    pfifo: Output_FIFO PORT MAP (
		aclr		=>	reset,
		clock		=> clk,
		data		=> pfifo_input, 
		rdreq		=> pfifo_rdreq,
		wrreq		=> pfifo_wreq,
		empty		=> open,
--		empty		=> pfifo_ept, ---debug using 
--		full		=> pfifo_full,
		full		=>open,
		q			=> pfifo_output,
		usedw		=> open
	);
    
    Afifo: Add_Fifo Port MAP
	(
		clock		=>clk,
		data		=>afifo_input,
		rdreq		=>afifo_rdreq,
		wrreq		=>afifo_wreq,
		empty		=>afifo_empty,
		full		=>open,
		q		    => afifo_output
	);

end Behav;